7 122 412

7,122,412 Title:

Method of fabricating a necked FINFET device

A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

What is claimed is:

1. A method of forming a field effect transistor (FET) structure in a silicon on insulator (SOI) layer, comprising the steps of: providing said SOI layer on a semiconductorsubstrate; defining a FET shape in said SOI layer with said FET shape having a necked channel region and having spaced wider silicon shapes disposed on opposite sides of said necked channel region, said necked channel region having a central portionwhere said necked channel region has its smallest width, and said necked channel region increasing progressively in width on each side of said central portion in directions away from said central portion toward each of said wider silicon shapes; forminga gate insulator layer on sides of said FET shape; forming a gate structure on said central portion of said necked channel region of said FET shape, with said gate structure engaging said gate insulator layer on each side of necked channel region; forming a source/drain region in said wider silicon shapes; forming an insulator spacer on sides of said FET shape not covered by said gate structure, and on sides of said gate structure; and forming a metal silicide layer on said source/drain regionresulting in said FET structure comprised with said necked channel region.

2. The method of claim 1, wherein an insulator component underlying said SOI layer is a silicon dioxide layer at a thickness between about 100to 2000 Angstroms.

3. The method of claim 1, wherein a silicon component of said SOI layer is a silicon layer at a thickness between about 100 to 2000 Angstroms.

4. The method of claim 1, wherein a hard mask insulator layer located overlying SOI layer is a silicon oxide layer, obtained via low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) procedures, ata thickness between about 10 to 500 Angatroms.

5. The method of claim 1, wherein said FET shape is defined in a hard mask insulator layer and in said SOI layer via an anisotropic RIE procedure using CHF.sub.3 as an etchant for said hard mask insulator layer and using Cl.sub.2 as etchant forsaid SOI layer.

6. The method of claim 1, wherein said smallest width of said necked channel region of said FET shape is between about 0.01 to 0.20 um.

7. The method of claim 1, wherein said gate insulator formed on sides of said FET shape, is a silicon dioxide layer at a thickness between about 6 to 100 Angatroms, obtained via temial oxidation procedures performed in an oxygen-steam ambientat a temperature between about 500 to 1200.degree. C.

8. The method of claim 1, wherein said gate structure is a polysilicon gate structure, formed at a thickness between about 300 to 2000 Angstroms.

9. The method of claim 1, wherein said source/drain region is formed via implantation of arsenic or phosphorous ions, at an entry between about 0.1 to 5 KeV, at a dose between about 1E19 to 5E20 atoms/cm.sup.2.

10. The method of claim 1, wherein said insulator spacer formed on sides of said FET shape and sides of said gate structure is a composite insulator spacer, comprised of an underlying silicon oxide component at a thickness between about 50 to200 Angstroms, and comprised of an overlying silicon nitride component at a thickness between about 100 to 1000 Angstrom.

11. The method of claim 1, wherein said metal silicide layer is chosen from a group containing such metal silicide layers as titanium silicide, tungsten silicide, nickel silicide, and cobalt silicide.

12. A method of forming a double gate FINFET structure in a SOI layer, comprising the steps of: forming said SOI layer on a semiconductor substrate; depositing a silicon oxide layer on said SOI layer; performing a first anisotropic dry etchprocedure that etches said silicon oxide layer and at least a silicon layer in said SOI layer to define an FET shape having a necked channel region and having spaced wider shapes disposed on opposite sides of said necked channel region, said neckedchannel region having a central portion where said necked channel region has its smallest width, and said necked channel region increasing progressively in width on each side of said central potion in direction away from said central portion toward eachof said wider shapes; growing a silicon dioxide gate insulator layer on sides of said FET shape; depositing a polysilicon layer over at least said central portion of said necked channel region and portions of said silicon dioxide gate insulator loverlocated on each side of said central portion of said necked channel region; performing a second anisotropic dry etch procedure that etches said polysilicon layer to define a polysilicon gate structure overlying said central portion of said neckedchannel region, and overlying said silicon dioxide gaze insulator layer located an each side of said necked channel region, resulting in a vertical double gate device configuration; removing said silicon oxide layer from said wider shapes; performingan ion implantation procedure to form a source/drain region in said wider shapes; depositing a composite insulator layer over at least sides of said FET shape not covered by said polysilicon gate structure and sides of said polysilicon gate structure,said composite insulator layer including an underlying silicon oxide layer and an overlying silicon nitride layer; performing a third anisotropic dry etch procedure to etch said composite insulator layer to form a composite insulator spacer on sides ofsaid FET shape not covered by said polysilion gate structure, and on sides of said polysilicon gate structure, said composite insulator spacer including an underlying silicon oxide component and an overlying silicon nitride component; and forming ametal silicide layer on said source/drain region resulting in said double gate FINFET structure comprised with said necked channel region and comprised with said composite insulator spacer.

13. The method of claim 12, wherein an insulator component of said SOI layer is a silicon dioxide layer at a thickness between about 100 to 2000 Angstroms.

14. The method of claim 12, wherein a silicon component of said SOI layer is a silicon layer at a thickness between about 100 to 2000 Angstroms.

15. The method of claim 12, wherein said silicon oxide layer is obtained via low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) procedures, at a thickness between about 10 to 500 Angstroms.

16. The method of claim 12, wherein said first anisotropic dry etch procedure used to define said FET shape in said silicon oxide layer and in said SOI layer is a anisotropic reactive ion etch (RIE) procedure performed using CHF3 as an etchantfor said silicon oxide layer and using Cl2 as a etchant for said SOI layer.

17. The method of claim 12, wherein said smallest width of said necked channel region of said FET shape is between about 0.01 to 0.20 um.

18. The method of claim 12, wherein said silicon dioxide gate insulator layer located on sides of said FET shape is a silicon dioxide layer formed to a thickness between about 6 to 100 Angstroms, via a thermal oxidation procedure performed inan oxygen-steam ambient at a temperature between about 500 to 1200.degree. C.

19. The method of claim 12, wherein said polysilicon layer is obtained via LPCVD procedures at a thickness between about 300 to 2000 Angstroms.

20. The method of claim 12, wherein said second anisotropic dry etch procedure used to define said polysilicon gate structure is an anisotropic RIE procedure performed using Cl.sub.2 as an etchant for polysilicon.

21. The method of claim 12, wherein said ion implantation procedure used to form said source/drain region is performed via implantation of arsenic or phosphorous ions at an energy between about 0.1 to 5 KeV, at a dose between about 1E19 to 5E20atoms/cm2.

22. The method of claim 12, wherein said composite insulator layer is comprised of said underlying silicon oxide layer obtained via LPCVD or PECVD procedures at a thickness between about 50 to 200 Angstroms, and comprised of an overlyingsilicon nitride layer obtained via LPCVD or PECVD procedures at a thickness between about 100 to 1000 Angatroms.

23. The method of claim 12, wherein said third anisotropic dry etch procedure used to define said composite spacer is an anisotropic RIE procedure performed using Cl.sub.2 or CF.sub.4 as an etchant for said silicon nitride layer, and usingCHF3, as an etchant for said silicon oxide layer.

24. The method of claim 12, wherein said metal silicide layer is chosen from a group of metal silicide layers such as titanium silicide, tungsten silicide, tungsten silicide, nickel silicide, or cobalt silicide.