6 518 841

6,518,841 Title:

Enhanced folded cascade voltage gain cell

A folded cascade voltage gain cell is implemented in a single stage by collapsing p-channel transistor branches receiving output currents from two sets of n-channel transistor branches and producing the output voltage into a single set of branches, summing the output currents from two sets of n-channel transistor branches in a single pair of nodes. While power consumption is only slightly improved over multistage folded cascade voltage gain cells, the circuit is implemented with fewer transistors and is therefore smaller and more reliable. Moreover, because only one gain stage is employed with a smaller number of internal nodes, the circuit's operation contains a smaller number of poles, and bandwidth is improved.

What is claimed is:

1. For use in an integrated circuit, a folded cascade voltage gain cell for providing improved reliability and operation comprising: a first set of branches containingtransistors of a first conductivity type, wherein an input voltage for the voltage gain cell is received at gates of the transistors within the first set of branches; a second set of branches containing transistors of the first conductivity type,wherein an output voltage for the voltage gain cell is received at gates of the transistors within the second set of branches; and a single set of branches containing transistors of a second conductivity type, wherein the single set of branchescontaining transistors of the second conductivity type receive output currents from the first and second sets of branches and produce the output voltage.

2. The folded cascade voltage gain cell as set forth in claim 1 wherein the single set of branches containing transistors of a second conductivity type further comprises: two p-channel transistors each coupled at a source thereof to both thefirst and second branches, wherein output signals at drains of the two p-channel transistors form the output voltage.

3. The folded cascade voltage gain cell as set forth in claim 2 wherein the first set of branches containing transistors of a first conductivity type further comprises: two n-channel transistors each receiving an input signal at a gate thereofand connected at a drain thereof to a source of one of the two p-channel transistors, wherein the input signals form the input voltage.

4. The folded cascade voltage gain cell as set forth in claim 3 wherein the second set of branches containing transistors of a first conductivity type further comprise: two n-channel transistors each receiving an output signal at a gate thereofand connected at a drain thereof to a source of one of the two p-channel transistors, wherein the output signals form the output voltage.

5. The folded cascade voltage gain cell as set forth in claim 4 wherein sources of the two n-channel transistors forming the first set of branches are connected by two series connected resistors each having a first resistance and sources of thetwo n-channel transistors forming the second set of branches are connected by two series connected resistors each having a second resistance, wherein a voltage gain of the folded cascade voltage gain cell equals the second resistance divided by the firstresistance.

6. The folded cascade voltage gain cell as set forth in claim 5 wherein drains of each of the n-channel transistors and sources of each of the p-channel transistors are each connected through one of two current sources to the power supplyvoltage.

7. The folded cascade voltage gain cell as set forth in claim 6 wherein sources of each of the n-channel transistors and drains of each of the p-channel transistors are each connected through a different current source to a ground voltage.

8. A folded cascade voltage gain cell comprising: a first pair of n-channel transistors each receiving an input signal at a gate thereof, wherein the input signals form a differential input voltage; a second pair of n-channel transistors eachreceiving an output signal at a gate thereof, wherein the output signals form a differential output voltage; and a single pair of p-channel transistors each receiving an output current from both one of the first pair of n-channel transistors and one ofthe second pair of n-channel transistors at a source thereof, the p-channel transistors producing the output signals at drains thereof.

9. The folded cascade voltage gain cell as set forth in claim 8 wherein the source of an upper signal p-channel transistor is connected to the drain of an upper signal n-channel transistor within the first pair and to a drain of an upper signaltransistor within the second pair, and wherein the source of a lower signal p-channel transistor is connected to the drain of a lower signal n-channel transistor within the first pair and to a drain of a lower signal transistor within the second pair.

10. The folded cascade voltage gain cell as set forth in claim 9 wherein sources of the first pair of n-channel transistors are connected by two series connected resistors each having a first resistance and sources of the second pair ofn-channel transistors are connected by two series connected resistors each having a second resistance, wherein a voltage gain of the folded cascade voltage gain cell equals the second resistance divided by the first resistance.

11. The folded cascade voltage gain cell as set forth in claim 10 wherein drains of each of the n-channel transistors and sources of each of the p-channel transistors are each connected through one of two current sources to the power supplyvoltage.

12. The folded cascade voltage gain cell as set forth in claim 11 wherein sources of each of the n-channel transistors and drains of each of the p-channel transistors are each connected through a different current source to a ground voltage.

13. The folded cascade voltage gain cell as set forth in claim 11 wherein each of the two current sources receives common mode feedback.

14. For use in an integrated circuit, a method of amplifying a signal comprising: receiving an input voltage at gates of transistors within a first set of branches for a folded cascade voltage gain cell, the first set of branches containingtransistors of a first conductivity type; receiving an output voltage at gates of transistors within a second set of branches for the folded cascade voltage gain cell, the second set of branches containing transistors of the first conductivity type; and receiving output currents from both the first and second sets of branches at a third set of branches for the folded cascade voltage gain cell, the third set of branches containing transistors of a second conductivity type and producing the outputvoltage.

15. The method as set forth in claim 14 wherein the step of receiving output currents from both the first and second sets of branches at a third set of branches for the folded cascade voltage gain cell further comprises: receiving the outputcurrents at two p-channel transistors each coupled at a source thereof to both the first and second branches, wherein output signals at drains of the two p-channel transistors form the output voltage.

16. The method as set forth in claim 15 wherein the step of receiving an input voltage at gates of transistors within a first set of branches for a folded cascade voltage gain cell further comprises: receiving the input signals at two n-channeltransistors each receiving an input signal at a gate thereof and connected at a drain thereof to a source of one of the two p-channel transistors, wherein the input signals form the input voltage.

17. The method as set forth in claim 16 wherein the step of receiving an output voltage at gates of transistors within a second set of branches for the folded cascade voltage gain cell further comprises: receiving the output voltage at twon-channel transistors each receiving an output signal at a gate thereof and connected at a drain thereof to a source of one of the two p-channel transistors, wherein the output signals form the output voltage.

18. The method as set forth in claim 17 further comprising: producing a voltage gain equal to a second resistance R.sub.2 for each of two series connected resistors connecting sources of the two n-channel transistors forming the second set ofbranches divided by a first resistance R.sub.1 for each of two series connected resistors connecting sources of the two n-channel transistors forming the first set of branches.

19. The method as set forth in claim 18 further comprising: receiving a power supply voltage at drains of each of the n-channel transistors and sources of each of the p-channel transistors through one of two current sources.

20. The method as set forth in claim 19 further comprising: receiving a ground voltage at sources of each of the n-channel transistors and drains of each of the p-channel transistors each through a different current source.